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16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
Integrated Device Technology, Inc.
IDT7210L
FEATURES:
* 16 x 16 parallel multiplier-accumulator with selectable accumulation and subtraction * High-speed: 20ns multiply-accumulate time * IDT7210 features selectable accumulation, subtraction, rounding and preloading with 35-bit result * IDT7210 is pin and function compatible with the TRW TDC1010J, TMC2210, Cypress CY7C510, and AMD AM29510 * Performs subtraction and double precision addition and multiplication * Produced using advanced CMOS high-performance technology * TTL-compatible * Available in topbraze DIP, PLCC, Flatpack and Pin Grid Array * Military product compliant to MIL-STD-883, Class B * Standard Military Drawing #5962-88733 is listed on this function * Speeds available: Commercial: L20/25/35/45/55/65 Military: L25/30/40/55/65/75
DESCRIPTION:
The IDT7210 is a high-speed, low-power 16 x 16-bit parallel multiplier-accumulator that is ideally suited for real-time digital signal processing applications. Fabricated using CMOS silicon gate technology, this device offers a very low-power alternative to existing bipolar and NMOS counterparts, with only 1/7 to 1/10 the power dissipation and exceptional speed (25ns maximum) performance. A pin and functional replacement for TRW's TDC1010J the IDT7210 operates from a single 5 volt supply and is compatible with standard TTL logic levels. The architecture of the IDT7210 is fairly straightforward, featuring individual input and output registers with clocked D-type flip-flop, a preload capability which enables input data to be preloaded into the output registers, individual three-state output ports for the Extended Product (XTP) and Most Significant Product (MSP) and a Least Significant Product output (LSP) which is multiplexed with the Y input. The XIN and YIN data input registers may be specified through the use of the Two's Complement input (TC) as either a two's complement or an unsigned magnitude, yielding a fullprecision 32-bit result that may be accumulated to a full 35-bit result. The three output registers - Extended Product (XTP), Most Most Significant Product (MSP) and Least Significant Product (LSP) - are controlled by the respective TSX, TSM and TSL input lines. The LSP output can be routed through YIN ports.
FUNCTIONAL BLOCK DIAGRAM
CLKX XIN (X15-X0)
16
ACC, SUB, RND, TC
4
CLKY
YIN (Y15-Y0/P15-P0)
16
XREGISTER
CONTROL REGISTER MULTIPLIER ARRAY
32
YREGISTER
+
+/-
TSL PREL
ACCUMULATOR
35
35
CLKP TSX
3
XTP REGISTER
3
MSP REGISTER
LSP REGISTER
16
TSM PREL
16
XTPOUT (P34-P32)
MSPOUT (P31-P16) IDT7210
2577 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1995 Integrated Device Technology, Inc.
AUGUST 1995
DSC-2018/7
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IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (Continued)
The Accumulate input (ACC) enables the device to perform either a multiply or a multiply-accumulate function. In the multiply-accumulate mode, output data can be added to or subtracted from previous results. When the Subtraction (SUB) input is active simultaneously with an active ACC, a subtraction can be performed. The double precision accumulated result is rounded down to either a single precision or single precision plus 3-bit extended result. In the multiply mode, the Extended Product output (XTP) is sign extended in the two's complement mode or set to zero in the unsigned mode. The Round (RND) control rounds up the Most Significant Product (MSP) and the 3-bit Extended Product (XTP) outputs. When Preload input (PREL) is active, all the output buffers are forced into a highimpedance state (see Preload truth table) and external data can be loaded into the output register by using the TSX, TSL and TSM signals as input controls.
PIN CONFIGURATIONS
X6 X5 X4 X3 X2 X1 X0 P0, P1, P2, P3, P4, P5, P6, P7, GND P8, P9, P10, P11, P12, P13, P14, P15, P16 P17 P18 P19 P20 P21 P22 P23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 C64-2 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 X7 X8 X9 X10 X11 X12 X13 X14 X15 TSL RND SUB ACC CLKX CLKY VCC TC TSX PREL TSM CLKP P34 P33 P32 P31 P30 P29 P28 P27 P26 P25 P24
P2, Y2 P3, Y3 P4, Y4 P5, Y5 P6, Y6 P7, Y7 GND GND P8, Y8 P9, Y9 P10, Y10 P11, Y11 P12, Y12 P13, Y13 P14, Y14 P15, Y15 P16
60 59 58 5756 55 54 53 5251 50 4948 47 46 45 44
P1, Y1 61 P0, Y0 62 X0 63 X1 64 X2 65 X3 66 X4 67 X5 68 X6 1 X7 2 X8 3 X9 4 X10 5 X11 6 X12 7 X13 8 X14 9
J68-1, L68-1 J68-1
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33
10 11 1213 14 1516 17 18 19 20 21 22 23 24 25 26
2577 drw 03
2577 drw 02
DIP TOP VIEW
P0, Y0 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64636261 605958575655 545352 515049 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P1, Y1 P2, Y2 P3, Y3 P4, Y4 P5, Y5 P6, Y6 P7, Y7 GND P8, Y8 P9, Y9 P10, Y10 P11, Y11 P12, Y12 P13, Y13 P14, Y14 P15, Y15
X15 TSL RND SUB ACC CLKX CLKY VCC VCC VCC VCC TC TSX PREL TSM CLKP P34
PLCC TOP VIEW
F64-1
P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31
17181920 212223242526 272829 303132
2577 drw 04
11.2
X15 TSL RND SUB ACC CLKX CLKY VCC TC TSX PREL TSM CLKP P34 P33 P32
FLATPACK TOP VIEW
2
IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
11 10 09 08 07 06 05 04 03 02 01 Pin 1 Designator A X13 X11 X9 X7 X5 X3 X1 Y0, P0 NC
NC X14 X12 X10 X8 X6 X4 X2 X0 Y1, P1 Y2, P2 B
X15 TSL
RND ACC CLKY SUB CLKX VCC
TC PREL CLKP P33 TSX TSM P34 P32 P30 P28 P26 NC P31 P29 P27 P25 P23 P21 P19 P17
G68-2
P24 P22 P20 P18
Y3, P3 Y4, P4 C
Y5, P5 Y6, P6 D
Y7, P7 GND E
Y8, P8 Y9, P9 F
Y10, P10 Y11, P11 G
Y12, P12 Y13, P13 H
Y14, P14 Y15, P15 J
P16 NC K
L
2577 drw 05
PGA TOP VIEW
PIN DESCRIPTIONS
Pin Name X0 - 15 Y0 - 15/ P0 - 15 P16 - 31 P32 - 34 CLKX CLKY CLKP TSX TSM TSL PREL ACC I/O I I/O I/O I/O I I I I I I I I Data Inputs Multiplexed I/O port. Y0 - 15 are data inputs and can be used to preload LSP register on PREL = 1. P0 - 15 are LSP register outputs - enabled by TSL. MSP register outputs - enabled by TSM. MSP register can be preloaded when PREL = 1. XTP register outputs - enabled by TSX. XTP register can be preloaded through these inputs when PREL = 1. Input data X0 - 15 loaded in X input register on CLKX rising edge. Input data Y0 - 15 loaded in Y input register on CLKY rising edge. Output data loaded into output register on rising edge of CLKP. TSX = 0 enables XTP outputs, TSX = 1 tristates P32 - 34 lines. TSM = 0 enables MSP outputs, TSM = 1 tristates P16 - 31 lines. TSL = 0 enables LSP outputs, TSL = 1 tristates P0 - 15 lines. When PREL= 1 data is input on P0 - 15 lines. When PREL = 0, inputs on these lines are ignored. This input is loaded into the control register on the rising edge of (CLKX + CLKY). When ACC = 1 and SUB = 0 an accumulate operation is performed. When ACC = 1 and SUB = 1, a subtract operation is performed. When ACC = 0, the SUB input is a don't care and the device acts as a simple multipler with no accumulation This input is loaded into the control register on the rising edge of (CLKX + CLKY). This input is active only when ACC = 1. When SUB = 1 the contents of the output register are subtracted from the result and stored back in the output register. When SUB = 0 the contents of the output register are added to the result and stored back in the output register This input is loaded into the control register on the rising edge of (CLKX + CLKY). When TC = 1, the X and Y input are assumed to be in two's complement form. When TC = 0, X and Y inputs are assumed to be in unsigned magnitude form This input is loaded into the control register on the rising edge of (CLKX + CLKY). RND is inactive when low. RND = 1, adds a "1" to the most significant bit of the LSP, to round MSP and XTP data
2577 tbl 01
Description
SUB
I
TC
I
RND
I
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IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRELOAD TRUTH TABLE
PREL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TSX 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TSM 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TSL 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 XTP Q Q Q Q Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z PL PL PL PL MSP Q Q Hi Z Hi Z Q Q Hi Z Hi Z Hi Z Hi Z PL PL Hi Z Hi Z PL PL LSP Q Hi Z Q Hi Z Q Hi Z Q Hi Z Hi Z PL Hi Z PL Hi Z PL Hi Z PL
NOTES ON TWO'S COMPLEMENT FORMATS
1. In two's complement notation, the location of the binary point that signifies the separation of the fractional and integer fileds is just after the sign, between the sign bit (-2) and the next significant bit for the multiplier inputs. This same format is carried over to the output format, except that the extended significance of the integer filed is provided to extend the utility of the accumulator. In the case of the output rotation, the output binary point is located between the2 and 21 bit positions. The location of the binary point is arbitrary, as long as there is consistency with both the input and output formats. The number filed can be considered entirely integer with the binary point just to the right of the least significant bit for the input, product and the accumulated sum. 2. When in the non-accumulating mode, the first four bits (P34 to P31) will all indicate the sign of the product. Additionally, the P30 term will also indicate the sign with one exception, when multiplying -1 x -1. With the additional bits that are available in this multiplier, the -1 x -1 is a valid operation that yields a +1 product. 3. In operations that require the accumulation of single products or sum of products, there is no change in format. To allow for a valid summation beyond that available for a single multiplication product, three additional significant bits (guard bits) are provided. This is the same as if the product was accumulated off-chip in a separate 35-bit wide adder. Taking the sign at the most significant bit position will guarantee that the largest number field will be used. When the accumulated sum only occupies the right hand portion of the accumulator, the sign will be extended into the lesser significant bit positions.
NOTES: 2577 tbl 02 Hi Z = Output buffers at high impedance (output disabled) Q = Output buffers at low impedance. Contents of output register will be transferred to output pins. PL = Output buffers at high impedance or output disabled. Preload data supplied externally at output pins will be loaded into the output register at the rising edge of CLKP.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating VCC Power Supply Voltage VTERM Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature IOUT DC Output Current Commercial -0.5 to +7.0 -0.5 to VCC +0.5V 0 to +70 -55 to +125 -55 to +125 50 Military -0.5 to +7.0 -0.5 to VCC +0.5V -55 to +125 -65 to +135 -65 to +150 50 Unit V V C C C mA
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 10 12 Unit pF pF
NOTE: 2577 tbl 04 1. This parameter is measured at characterization and not 100%tested.
NOTE: 2577 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C; Military: VCC = 5V 10%, TA = -55C to +125C)
Commercial Symbol Parameter VIH Input High Voltage VIL |ILI| |ILO| VOH VOL(4) IOS ICC (2) Input Low Voltage Input Leakage Current Output Leakage Current Output HIGH Voltage Output LOW Voltage Output Short Circuit Current Operating Power Supply Current Test Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max., VIN = 0V to VCC VCC = Max., Outputs Disabled VOUT = 0 to VCC VCC = Min., IOH = -2.0mA VCC = Min., IOL = 4mA VCC = Max., V0 GND VCC = Max., Outputs Enabled f= 10MHz(2) CL = 50 pF VIN VIH, VIN VIL VIN VCC -0.2V, V
IN
Military Min. 2.0 -- -- -- 2.4 -- -20 -- Typ.(1) -- -- -- -- -- -- -- 45 Max. -- 0.8 10 10 -- 0.4 -100 110 Unit V V A A V V mA mA
Conditions(5)
Min. 2.0 -- -- -- 2.4 -- -20 --
Typ.(1) -- -- -- -- -- -- -- 45
Max. -- 0.8 10 10 -- 0.4 -100 90
ICCQ1 ICCQ2
Quiescent Power Supply Current Quiescent Power Supply Current
-- -- --
20 4 --
30 10 6
-- -- --
20 4 --
30 12 8
mA mA mA/ MHz
0.2V
ICC/f (2,3) Increase in Power Supply Current MHz
VCC = Max., Outputs Disabled
2577 tbl 05 NOTES: 1. Typical implies VCC = 5V and TA = +25C. 2. ICC is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range: ICC = 90+ 6(f -10)mA, where f = operating frequency in MHz. For the military range, ICC = 110 + 8(f -10). f = operating frequency in MHz, f = 1/tMA. 3. For frequencies greater than 10MHz, guaranteed by design, not production tested. 4. IOL = 4mA for tMA > 55ns. 5. For conditions shown as Max. or Min., use appropriate value specified under electrical characteristics.
AC ELECTRICAL CHARACTERISTICS COMMERCIAL (VCC = 5V 10%, TA = 0 to +70C)
Symbol t MA tD t ENA t DIS tS tH t PW t HCL Parameter Multiply-Accumulate Time(2) Output Delay (2) 3-State Enable Time 3-State Disable Time(1) Input Register Set-up Time Input Register Hold Time Clock Pulse Width Relative Hold Time 7210L20 Min. Max. 2.0 20 2.0 18 -- 18 -- 18 10 -- 3 -- 9 -- 0 -- 7210L25 Min. Max. 2.0 25 2.0 20 - 20 - 20 12 - 3 - 10 - 0 - 7210L35 Min. Max. 2.0 35 2.0 25 - 25 - 25 12 - 3 - 10 - 0 - 7210L45 Min. Max. 2.0 45 2.0 25 - 25 - 25 15 - 3 - 15 - 0 - 7210L55 Min. Max. 2.0 55 2.0 30 - 30 - 30 20 - 3 - 20 - 0 - 7210L65 Min. Max. Unit 2.0 65 ns 2.0 35 ns - 30 ns - 30 ns 25 - ns 3 - ns 25 - ns 0 - ns
2577 tbl 06
NOTES: 1. Transition is measured 500mV from steady state voltage. 2. Minimum delays guaranteed but not tested
AC ELECTRICAL CHARACTERISTICS MILITARY (VCC = 5V 10%, TA = -55 to +125C)
Symbol t MA tD t ENA t DIS tS tH t PW t HCL Parameter Multiply-Accumulate Time(2) Output Delay (2) 3-State Enable Time 3-State Disable Time(1) Input Register Set-up Time Input Register Hold Time Clock Pulse Width Relative Hold Time 7210L25 Min. Max. 2.0 25 2.0 20 -- 20 -- 20 12 -- 3 -- 10 -- 0 -- 7210L30 Min. Max. 2.0 30 2.0 20 - 20 - 20 12 - 3 - 10 - 0 - 7210L40 Min. Max. 2.0 40 2.0 25 - 25 - 25 15 - 3 - 15 - 0 - 7210L55 Min. Max. 2.0 55 2.0 30 - 30 - 25 20 - 3 - 20 - 0 - 7210L65 Min. Max. 2.0 65 2.0 35 - 30 - 30 25 - 3 - 25 - 0 - 7210L75 Min. Max. Unit 2.0 75 ns 2.0 35 ns - 35 ns - 30 ns 25 - ns 3 - ns 25 - ns 0 - ns
2577 tbl 07
NOTES: 1. Transition is measured 500mV from steady state voltage. 2. Minimum delays guaranteed but not tested 11.2
5
IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INPUT
CONTROL AND DATAIN
tS INPUT CLOCK OUTPUT CLOCK
tH tPW tMA tPW tHCL
PRELOAD
THREE-STATE CONTROL tDIS OUTPUT tENA
HIGH IMPEDANCE DATAOUT
tDIS
tS
tH
PRELOAD IN DATA
tENA
DATAOUT
tD
Figure 1. Timing Diagram
11.2
6
BINARY POINT
X 15 X 14 X 13 X 12 X 11 X 10 X9 X7 2-8 2-10 2 -11 2-12 2 -13 2-14 2 -15 Y5 2-10 2 -11 2-12 2 -13 2-14 2 -15 P8 P7 P6 P5 P4 DIGIT VALUE P3 P2 P1 Y4 Y3 Y1 Y2 Y0 SIGNAL Y7 2-8 2 -9 Y6 2 -9 DIGIT VALUE X5 X3 X1 2-2 Y8 2 -7 2 -3 2-4 2 -5 2-6 2 -7
X8
X6
X4
X2
X0
SIGNAL
-20 2 -1
Y 15 Y 14 Y 13 Y 12 Y 11 Y 10 Y9 2-2 2 -3 2-4 2 -5 2-6
X
-20 2 -1
P34 P 33 P 32 P 31 P 30 P 29 P 28 P 27 P 26 P 25 P 24 P 23 P 22 P 21 P20 P 19 P 18 P 17 P 16 P 15 P 14 P 13 P 12 P 11 P10 P 9 2 -1 2 MSP LSP 2 2 2
-2
P0
SIGNAL
= 2 -3
-4
-24 2 3
22
21
20
2 -5
-6
2 -7
-8
2 -9
DIGIT 2-10 2 -11 2-12 2 -13 2-14 2 -15 2-16 2 -17 2-18 2 -19 2-20 2 -21 2-22 2 -23 2-24 2 -25 2-26 2 -27 2-28 2 -29 2-30 VALUE
XTP
IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
2577 drw 10
Figure 2. Fractional Two's Complement Notation.
11.2
X8 X7 2 Y7 2
-9 -9
BINARY POINT
X 15 X 14 X 13 X 12 X11 X 10 X9 X5 X3 2 Y8 Y5
-8 -3
X6
X4
X2
X1
X0
SIGNAL DIGIT VALUE
2 Y6 Y4 Y3
-1
2 -2 2 2 -6 2
2 -4
-5
-7
-8
2 -10 2-11 2 -12 2-13 2 -14 2-15 2 -16 Y2 Y1 Y0
X 2
-3
Y 15 Y 14 Y 13 Y 12 Y 11 Y 10 Y 9 2 -4 2 2
-5
SIGNAL DIGIT VALUE P8 P7 P6 P5 P4 P3 P2 P1 P0 SIGNAL
2
-1
2 -2
2 -6
-7
2 -10 2-11 2 -12 2-13 2 -14 2-15 2 -16
= 2
-3
P 34 P 33 P 32 P 31 P 30 P 29 P 28 P 27 P 26 P 25 P 24 P 23 P 22 P 21 P 20 P 19 P 18 P 17 P 16 P 15 P 14 P 13 P 12 P 11 P 10 P 9 2 -4 2 2 2
-5
22
2
1
20
2
-1
2 -2
2 -6
-7
2 -8
-9
DIGIT 2 -10 2-11 2 -12 2-13 2 -14 2-15 2 -16 2-17 2 -18 2-19 2 -20 2-21 2 -22 2-23 2 -24 2-25 2 -26 2-27 2 -28 2-29 2 -30 2-31 2 -32 VALUE MSP LSP
XTP
2577 drw 11
Figure 3. Fractional Unsigned Mgnitude Notation
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7
BINARY POINT
X15 X14 X13 X12 X11 X10 X9 X7 27 Y7 27 P7 2
7
X8 X5 25 Y5 25 P5
6
X6 X3 23 Y3 23 P4 2
5
X4 24 Y4 24 22 Y2 22 P3 2
4
X2
X1 21 Y1 21
X0 20 Y0 20
SIGNAL DIGIT VALUE SIGNAL DIGIT VALUE
-215 214 Y15 Y14 Y13 Y12 Y11 Y10 Y9 X -215 214 P8 2
8
213 Y8 28 P6 2 26 Y6
212
211
210
29
28
26
213
212
211
210
29
P34 P33 P32 P31 P30 P29 P28 P27 P 26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P 16 P15 P14 P13 P12 P11 P10 P9 2 MSP
31
P2 2
3
P1 2
2
P0 2
1
SIGNAL 2
0
= 2 2 2 2 2 2 2 2 2 2 2 2
30 29
-2
34
2
33
2
32
2
28
27
2
26
25
2
24
23
2
22
21
2
20
19
2
18
17
2
16
15
2
14
13
2
12
11
2
10
9
DIGIT VALUE
XTP
LSP
2577 drw 12
IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
Figure 4. Integer Two's Complement Notation
11.2
BINARY POINT X 15 X 14 X 13 X 12 X 11 X 10 X 9 215 214 213 212 211 210 29 Y 15 Y 14 Y 13 Y 12 Y 11 Y 10 Y 9 X 215 214 213 212 211 210 29 28 P8 2 MSP
22
X8 28 Y8
X7 27 Y7 27 P7
X6 26 Y6 26 P6
X5 25 Y5 25 P5
X4 24 Y4 24 P4
X3 23 Y3 23 P3
X2 22 Y2 22 P2
X1 21 Y1 21 P1
X0 20 Y0 20 P0
SIGNAL DIGIT VALUE SIGNAL DIGIT VALUE SIGNAL
P 34 P 33 P 32 P 31 P 30 P 29 P 28 P 27 P 26 P 25 P24 P 23 P22 P 21 P20 P 19 P18 P 17 P 16 P 15 P 14 P 13 P 12 P 11 P 10 P 9 231 2 2 2 2
30
= 229
28
234 233
2
32
227
26
2 25
24
2 23
2 21
2
20
2 19
2
18
2 17
2
16
215
2
14
213
2
12
211
2
10
29
2
8
27 LSP
2
6
25
2
4
23
2
2
21
2
0
DIGIT VALUE
XTP
Figure 5. Integer Unsigned Magnitude Notation
2577 drw 13
MILITARY AND COMMERCIAL TEMPERATURE RANGES
8
IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Open
2577 lnk 09
Switch
Closed
DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
2577 drw 06
SET-UP, HOLD AND RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
2577 drw 07
PULSE WIDTH
tH
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
2577 drw 08
tSU
tH
PROPAGATION DELAY
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
2577 drw 09
ENABLE AND DISABLE TIMES
ENABLE DISABLE 3V CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 0V
2577 drw 10
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
1.5V tPLZ 3.5V 1.5V tPHZ 0.3V VOH 0V 3.5V 0.3V VOL
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
11.2
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IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXX Device Type A Power 999 Speed A Package X Process/ Temperature Range Blank B Commercial (0C to +70C) Military (-55C to +125C) Compliant to MIL-STD-883, Class B Topbraze DIP Plastic Leaded Chip Carrier Flatpack Pin Grid Array
C J F G
Com'l. 20 25 35 45 55 65 L 7210
Mil. 25 30 40 55 65 75
Speed in Nanoseconds
Low Power 16 x 16 Parallel Multiplier Accumulator
2577 drw 11
11.2
10

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